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Single, Dual, Quad General Purpose Micropower, RRIO Operational Amplifiers
ISL28114, ISL28214, ISL28414
The ISL28114, ISL28214, and ISL28414 are single, dual, and quad channel general purpose micropower, rail-to-rail input and output operational amplifiers with supply voltage range of 1.8V to 5.5V. Key features are a low supply current of 360A maximum per channel at room temperature, a low bias current and a wide input voltage range, which enables the ISL28x14 devices to be excellent general purpose op-amps for a wide range of applications. The ISL28114 is available in the SC70-5 and SOT23-5 packages, the ISL28214 is in the MSOP8, SO8 packages, and the ISL28414 is in the TSSOP14, SOIC14 packages. All devices operate over the extended temperature range of -40C to +125C.
ISL28114, ISL28214, ISL28414
Features
* Low Current Consumption . . . . . . . . . . . . . 360A * Wide Supply Range. . . . . . . . . . . . . 1.8V to 5.5V * Gain Bandwidth Product . . . . . . . . . . . . . . 5MHz * Input Bias Current . . . . . . . . . . . . . . 20pA, Max. * Operating Temperature Range . . .-40C to +125C * Packages - ISL28114 (Single) . . . . . . . . . SC70-5, SOT23-5 - ISL28214 (Dual) . . . . . . . . . . . . . MSOP8, SO8 - ISL28414 (Quad). . . . . . . . . SOIC14, TSSOP14
Applications*(see page 15)
* Power Supply Control/Regulation * Process Control * Signal Ban/Buffers * Active Filters * Current Shunt Sensing * Trans-impedance Amp
Typical Application
RF LOAD RINRSENSE 10k RIN+ 10k RREF+ 100k VREF IN+ IN100k +5V V+ ISL28x14 V-
-
VOUT
+
GAIN = 10
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
December 22, 2009 FN6800.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL28114, ISL28214, ISL28414
Ordering Information
PART NUMBER (Note 2) ISL28114FEZ-T7 (Note 1) ISL28114FEZ-T7A (Note 1) ISL28114FHZ-T7 (Note 1) ISL28114FHZ-T7A (Note 1) ISL28214FUZ ISL28214FUZ-T7 (Note 1) ISL28214FBZ ISL28214FBZ-T7 (Note 1) ISL28214FBZ-T13 (Note 1) ISL28414FVZ ISL28414FVZ-T7 (Note 1) ISL28414FVZ-T13 (Note 1) ISL28414FBZ ISL28414FBZ-T7 (Note 1) ISL28414FBZ-T13 (Note 1) NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28114, ISL28214, ISL28414. For more information on MSL please see techbrief TB363. BKA BKA BDBA BDBA 8214Z 8214Z 28214 FBZ 28214 FBZ 28214 FBZ 28414 FVZ 28414 FVZ 28414 FVZ 28414 FBZ 28414 FBZ 28414 FBZ PART MARKING PACKAGE (Pb-Free) 5 Ld SC-70 5 Ld SC-70 5 Ld SOT-23 5 Ld SOT-23 8 Ld MSOP 8 Ld MSOP 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 14 Ld TSSOP 14 Ld TSSOP 14 Ld TSSOP 14 Ld SOIC 14 Ld SOIC 14 Ld SOIC P5.049 P5.049 MDP0038 MDP0038 M8.118A M8.118A M8.15E M8.15E M8.15E MDP0044 MDP0044 MDP0044 MDP0027 MDP0027 MDP0027 PKG. DWG. #
Pin Configurations
ISL28114 (5 LD SC-70) TOP VIEW
IN+ VSIN1 2 3 4 OUT 5 VS+
ISL28114 (5 LD SOT-23) TOP VIEW
OUT VSIN+ 1 2 3 4 IN5 VS+
ISL28214 (8 LD MSOP, 8 LD SOIC) TOP VIEW
OUT_A IN-_A IN+_A VS1 2 3 4 8 7 6 5 VS+ OUT_B IN-_B IN+_B
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FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Pin Configurations (Continued)
ISL28414 (14 LD TSSOP, 14 LD SOIC) TOP VIEW
OUT_A 1 IN-_A 2 IN+_A 3 VS+ 4 IN+_B 5 IN-_B 6 OUT_B 7 14 OUT_D 13 IN-_D 12 IN+_D 11 VS10 IN+_C 9 IN-_C 8 OUT_C
Pin Descriptions
PIN NO. TSSOP14, PIN NAME SC70-5 SOT23-5 MSOP8, SO8 14 LD SOIC OUT OUT_A OUT_B OUT_C OUT_D 4 1 1 7 1 7 8 14 DESCRIPTION Output
V+
OUT
VCIRCUIT 1
VS-
2
2
4
11
Negative supply voltage
V CAPACITIVELY TRIGGERED ESD CLAMP VCIRCUIT 2
IN+ IN+_A IN+_B IN+_C IN+_D ININ-_A IN-_B IN-_C IN-_D VS+
1
3 3 5 3 5 10 12
Positive Input
V+
IN-
IN+
3
4 2 6 2 6 9 13 4
Negative Input
VCIRCUIT 3
5
5
8
Positive supply voltage
See Circuit 2
3
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Absolute Maximum Ratings (TA = +25C)
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . Differential Input Current . . . . . . . . . . . . . . . . . . . . Differential Input Voltage . . . . . . . . . . . . . . . . . . . . Input Voltage. . . . . . . . . . . . . . . . . . V- - 0.5V to V+ ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . Machine Model (ISL28114, ISL28214) . . . . . . . . . . Machine Model (ISL28414) . . . . . . . . . . . . . . . . . . Charged Device Model . . . . . . . . . . . . . . . . . . . . . . .6.5V . 1V/s . 20mA . 0.5V + 0.5V 4000V . 350V . 400V 2000V
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 5 Ld SC-70 (Notes 4, 5) . . . . . . . . 250 N/A 5 Ld SOT-23 (Notes 4, 5) . . . . . . . 225 N/A 8 Ld MSOP (Notes 4, 5) . . . . . . . . 180 100 8 Ld SO Package (Notes 4, 5) . . . . 126 90 14 Ld TSSOP Package (Notes 4, 5) 120 40 14 Ld SOIC Package (Notes 4, 5) . 90 50 Ambient Operating Temperature Range. . . . -40C to +125C Storage Temperature Range . . . . . . . . . . . -65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C, unless otherwise specified. CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT
PARAMETER DC SPECIFICATIONS VOS
DESCRIPTION
Input Offset Voltage
-5 -6
0.5
5 6
mV mV V/C pA pA pA pA pA V dB dB dB dB V V
TCVOS IOS IB
Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current
-40C to +125C
2 1
10 30 20 100
ISL28114
-20 -100
3
ISL28214, ISL28414
-20 -50
3
20 50 5.1
Common Mode Input Voltage Range CMRR Common Mode Rejection Ratio VCM = -0.1V to 5.1V
- 0.1 72 70
PSRR
Power Supply Rejection Ratio
VS = 1.8V to 5.5V
71 70
VOH
Output Voltage Swing, High
RL = 10k
4.985 4.98
4.993
VOL
Output Voltage Swing, Low
RL = 10k
13
15 20
mV mV V A A
V+ IS
Supply Voltage Supply Current per Amplifier RL = OPEN
1.8 300
5.5 360 400
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FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Electrical Specifications
VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C, unless otherwise specified. (Continued) CONDITIONS RL = 10 to VRL = 10 to V+ MIN (Note 6) TYP -31 26 MAX (Note 6) UNIT mA mA
PARAMETER ISC+ ISC-
DESCRIPTION Output Source Short Circuit Current Output Sink Short Circuit Current
AC SPECIFICATIONS GBWP Gain Bandwidth Product VS = 2.5V AV = 100, RF = 100k, RG = 1k, RL = 10k to VCM VS = 2.5V f = 0.1Hz to 10Hz VS = 2.5V f = 1kHz VS = 2.5V f = 1kHz 5 MHz
eN VP-P eN iN ZIN Cin
Peak-to-Peak Input Noise Voltage Input Noise Voltage Density Input Noise Current Density Input Impedance Differential Input Capacitance Common Mode Input Capacitance
12 40 8 1012
VP-P nV/(Hz) fA/(Hz) pF pF
VS = 2.5V f = 1MHz
1.0 1.3
TRANSIENT RESPONSE SR tr, tf, Small Signal Slew Rate Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% ts Settling Time to 0.1%, 4VP-P Step VOUT = 0.5V to 4.5V VS = 2.5V AV = +1, VOUT = 0.05VP-P, RF = 0, RL = 10k, CL = 15pF VS = 2.5V AV = +1, RF = 0, RL = 10k, CL = 1.2pF 2.5 37 42 V/s ns ns
5.6
s
NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
5
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Typical Performance CurvesVS = 2.5V, VCM = 0V, RL = Open, unless otherwise
specified.
INPUT NOISE VOLTAGE (nV/Hz) 50 40 30 20 IBIAS (pA) 10 0 -10 -20 -30 -40 SIMULATION -50 -40 -20 0 20 10,000 V+ = 2.5V AV = 1
1000
100
40
60
80
100 120 140
10
1
10
100
1k
10k
100k
TEMPERATURE (C)
FREQUENCY (Hz)
FIGURE 1. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL DENSITY
120 100 OPEN LOOP GAIN (dB) 80 60 40 20 0 -20 V+ = 0.9V RL = 100k -40 CL = 10pF -60 SIMULATION -80 0.1 1 10 100 PHASE GAIN
20 0 OPEN LOOP GAIN (dB) -20 -40 -60 -80 -100 -120 -140 -160 1k 10k 100k FREQUENCY (Hz) 1M -180 10M 100M PHASE ()
120 100 80 60 40 20 0 -20 V+ = 0.9V RL = 100k -40 CL = 10pF -60 SIMULATION -80 0.1 1 10 PHASE GAIN
20 0 -20 -40 -60 -80 -100 -120 -140 -160 100 1k 10k 100k FREQUENCY (Hz) 1M -180 10M 100M PHASE ()
FIGURE 3. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 100k, CL = 10pF, VS = 0.9V
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 100k, CL = 10pF, VS = 2.5V
80 70 60 CMRR (dB) PSRR (dB) 50 40 30 20 10 0 0.01 SIMULATION 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M
90 80 70 60 50 40 30 PSRR- VS = 0.9V
PSRR+ VS = 0.9V PSRR+ VS = 2.5V PSRR- VS = 2.5V
RL = INF 20 CL = 4pF AV = +1 10 VCM = 100mVP-P 0 100 1k 10k 100k FREQUENCY (Hz)
1M
10M
FIGURE 5. CMRR vs FREQUENCY (SIMULATED DATA)
FIGURE 6. PSRR vs FREQUENCY, VS = 0.9V, 2.5V
6
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Typical Performance CurvesVS = 2.5V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
1 NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 VS = 2.5V CL = 4pF -7 AV = +1 -8 R = 10k
L
70 60 50
GAIN (dB)
AV = 1000
Rg = 100, Rf = 100k Rg = 1k, Rf = 100k
40 30 20 10 0
AV = 100
AV = 10 Rg = 10k, Rf = 100k AV = 1 Rg = OPEN, Rf = 0 100 1k 10k
V+ = 2.5V CL = 4pF RL = 10k VOUT = 50mVP-P
VOUT = 10mVP-P VOUT = 50mVP-P VOUT = 100mVP-P VOUT = 200mVP-P VOUT = 500mVP-P VOUT = 1VP-P 10k 100k 1M 10M 100M FREQUENCY (Hz)
-10 10
100k
1M
10M
100M
-9 100
1k
FREQUENCY (Hz)
FIGURE 7. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
FIGURE 8. FREQUENCY RESPONSE vs VOUT
1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 V+ = 2.5V CL = 4pF AV = +1 RL = 4.99k RL = 1k RL = 499 RL = 100 100k 1M 10M 100M
7 6 5 4 3 2 1 0 -1 -2 -3 1k 10k CL = 26pF CL = 4pF 100k FREQUENCY (Hz) 1M 10M VS = 2.5V RL = 10k AV = +1 VOUT = 50mVP-P
CL = 1004pF CL = 474pF CL = 224pF CL = 104pF
-8 V OUT = 50mVP-P -9 100 1k 10k
FREQUENCY (Hz)
FIGURE 9. GAIN vs FREQUENCY vs RL
FIGURE 10. GAIN vs FREQUENCY vs CL
1 NORMALIZED GAIN (dB) 0 CROSSTALK (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 10k 100k VS = 2.5V VS = 1.75V VS = 1.25V VS = 0.9V 1M FREQUENCY (Hz) 10M 100M CL = 4pF RL = 10k AV = +1 VOUT = 50mVP-P
140 120 100 80 60 40 20 VS = 2.5V RL-DRIVER = INF RL-RECEIVER = 10k CL = 4pF AV = +1 VSOURCE = 1VP-P 100 1k 10k 100k 1M 10M
0 10
FREQUENCY (Hz)
FIGURE 11. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 12. CROSSTALK, VS = 2.5V
7
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Typical Performance CurvesVS = 2.5V, VCM = 0V, RL = Open, unless otherwise
specified. (Continued)
3 2 LARGE SIGNAL (V) 1 0 -1 -2 -3 VS = 0.9V RL = 10k CL = 15pF AV = +1 VOUT = RAIL VS = 2.5V 30 20 SMALL SIGNAL (mV) 10 0 -10 -20 -30 -40 0 80 160 240 320 400 480 560 640 720 800 TIME (ns) VS = 2.5V RL = 10k CL = 15pF AV = +1 VOUT = 50mVP-P
0
1
2
3
4 5 6 TIME (s)
7
8
9
10
FIGURE 13. SMALL SIGNAL TRANSIENT RESPONSE, VS = 2.5V
FIGURE 14. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = 0.9V, 2.5V
0.1 0 -0.1 INPUT (V) -0.2 -0.3 -0.4 -0.5 -0.6 0 INPUT RL = INF CL = 15pF AV =10 Rf = 9.09k, Rg = 1k OUTPUT @ VS = 0.9V OUTPUT @ VS = 2.5V
0.5 0 -0.5 OUTPUT (V) INPUT (V) -1.0 -1.5 -2.0 -2.5 -3.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0 TIME (ms)
0.6 0.5 0.4 0.3 0.2 0.1 0 INPUT -0.1 0 OUTPUT @ VS = 2.5V
3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0 TIME (ms) OUTPUT (V)
OUTPUT @ VS=0.9V RL = INF CL = 15pF AV =10 Rf = 9.09k, Rg = 1k
FIGURE 15. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = 0.9V, 2.5V
FIGURE 16. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = 0.9V, 2.5V
80
OVERSHOOT (%)
VS = 2.5V 70 RL = 10k AV = 1 60 VOUT = 50mVP-P
O V ER SH O O V O ER T SH + O O T -
50 40 30 20 10 0 10
100 1k CAPACITANCE (pF)
10k
FIGURE 17. % OVERSHOOT vs LOAD CAPACITANCE, VS = 2.5V
8
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Applications Information
Functional Description
The ISL28114, ISL28214 and ISL28414 are single dual and quad, CMOS rail-to-rail input, output (RRIO) micropower operational amplifiers. They are designed to operate from single supply (1.8V to 5.5V) or dual supply (0.9V to 2.75V). The parts have an input common mode range that extends 100mV above and below the power supply voltage rails. The output stage can swing to within 15mV of the supply rails with a 10k load.
Power Dissipation
It is possible to exceed the +125C maximum junction temperatures under certain load, power supply conditions and ambient temperature conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1:
T JMAX = T MAX + JA xPD MAXTOTAL (EQ. 1)
Input ESD Diode Protection
All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (see "Pin Descriptions - Circuit 1" on page 3). For applications where the input differential voltage is expected to exceed 0.5V, an external series resistor must be used to ensure the input currents never exceed 20mA (see Figure 18).
where: * PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) * PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX PD MAX = V S x I qMAX + ( V S - V OUTMAX ) x --------------------------R
L
(EQ.2)
where: * TMAX = Maximum ambient temperature
VIN RIN + RL VOUT
* JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of 1 amplifier * VS = Total supply voltage * IqMAX = Maximum quiescent supply current of 1 amplifier * VOUTMAX = Maximum output voltage swing of the application * RL = Load resistance
FIGURE 18. INPUT CURRENT LIMITING
Although the amplifier is fully protected, high input slew rates that exceed the amplifier slew rate (2.5V/s) may cause output distortion.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28114, ISL28214 and ISL28414 are immune to output phase reversal, even when the input voltage is 1V beyond the supplies.
ISL28114, ISL28214 and ISL28414 SPICE Model
Figure 20 shows the SPICE model schematic and Figure 21 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC parameters are IOS, total supply current and output voltage swing. The model uses typical parameters given in the "Electrical Specifications" Table beginning on page 4. The AVOL is adjusted for 90dB with the dominate pole at 125Hz. The CMRR is set 72dB, f = 80kHz). The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25C. Figures 22 through 29 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Large Signal 5V Step Response and CMRR and Open Loop Gain Phase.
Unused Channels
If the application requires less than all amplifiers one channel, the user must configure the unused channel(s) to prevent it from oscillating. The unused channel(s) will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the inverting input and ground the positive input (as shown in Figure 19).
+
FIGURE 19. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
9
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as "Licensee", a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee's company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided "AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE." In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice.
.
10
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
En Vin+ + R21 500E3
Voltage Noise Stage
+
28 29 DN D13
V9 -
V++ + 2 V1 1E-6V I2 5E-3 G1A
0.00035V En Vc Vmid 1 M14
+
R22 5E11 CinDiff R23 5E11 1.02pF
+ -
+ In+
R2 R1 1.0004 1.0004 3 4 R3 10 7 R4 10 6 M15
+ 14
RA1 1 R9 100 RA2 1 DX D1 DX D2 15
R10 1E9
M16
9 R5 10 11 R7 1
8
10 R6 10 12 R8 1
M17
4 5 Vc Vmid
EOS 5
G2A
Vin-
Cin1 1.26pF
Cin2 1.26pF
I1 5E-3
IOS 25E-12
+ 1E-6V V2
V--
Input Stage
V++ 4 D3 DX + V3 - 0.61V 16 Vg D5 DX + V5 - 0.604V 636.658E3 R13 C2 2.0nF
G1
G3 R11 1
+ -
17
+ -
19
5 Vc
Vmid Vc
Vmid
G2 + 18 V4 0.61V
R12 1
G4
C3 0.604V + V6 20 D6 DX 2.0nF R14 636.658E3
E4
+ -
V-VCM V++
D4 DX
VCM
1ST Gain Stage (Cont)
2nd Gain Stage
Mid Supply Ref
Common Mode Gain Stage
G7 V+ V+
C4 10pF
+ -
+ -
E2
+ -
D9 DX 26 27
D10 DX V7 + -
Vg Vmid V-
ISY 300uA
R17 2652.66 23
D7
DX
24
0.08V D8 DX V8 25 0.08V G12 D11 DY + -
R18 2652.66 +
+
E3 V-
+
G8
C3 10pF
+ G9
+ G10
D12 DY
V--
Supply Isolation Stage
Pole Stage
FIGURE 20. SPICE SCHEMATIC
Output Stage
11
+ -
+ -
+ -
+ 1ST Gain Stage
G5 L1 1.9895 21 R15 1E6 Vg R16 1E6 22 L2 1.9895
13
V-VCM
V++
+ -
Vmid
G6
+ -
+ -
V--
G11
+
VOUT
R19 50 VOUT
R20 50
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
* source ISL28114_SPICEmodel * Revision C, LaFontaine October 7th 2009 * Model for Noise, supply currents, CMRR 72dB f=80kHz ,AVOL 90dB f=125Hz * SR = 2.5V/us, GBWP 5MHz, 2nd pole 6MHz Output voltage clamp and short ckt I limit *Copyright 2009 by Intersil Corporation *Refer to data sheet "LICENSE STATEMENT" Use of *this model indicates your acceptance with the *terms and provisions in the License Statement. * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28114subckt Vin+ Vin- V+ VVOUT * source ISL28114_DS rev1 * *Voltage Noise E_En VIN+ EN 28 0 1 D_D13 29 28 DN V_V9 29 0 .00035 R_R21 28 0 500E3 TC=0,0 * *Input Stage M_M14 3 1 5 5 NCHANNELMOSFET M_M15 4 VIN- 6 6 NCHANNELMOSFET M_M16 11 VIN- 9 9 PMOSISIL M_M17 12 1 10 10 PMOSISIL I_I1 7 V-- DC 5e-3 I_I2 V++ 8 DC 5e-3 I_IOS VIN- 1 DC 25e-12 G_G1A V++ 14 4 3 1404 G_G2A V-- 14 11 12 1404 V_V1 V++ 2 1e-6 V_V2 13 V-- 1e-6 R_R1 3 2 1.0004 TC=0,0 R_R2 4 2 1.0004 TC=0,0 R_R3 5 7 10 TC=0,0 R_R4 7 6 10 TC=0,0 R_R5 9 8 10 TC=0,0 R_R6 8 10 10 TC=0,0 R_R7 13 11 1 TC=0,0 R_R8 13 12 1 TC=0,0 R_RA1 14 V++ 1 TC=0,0 R_RA2 V-- 14 1 TC=0,0 C_CinDif VIN- EN 1.02E-12 TC=0,0 C_Cin1 V-- EN 1.26e-12 TC=0,0 C_Cin2 V-- VIN- 1.26e-12 TC=0,0 * *1st Gain Stage G_G1 V++ 16 15 VMID 334.753e-3 G_G2 V-- 16 15 VMID 334.753e-3 V_V3 17 16 .61 V_V4 16 18 .61 D_D1 15 VMID DX D_D2 VMID 15 DX D_D3 17 V++ DX D_D4 V-- 18 DX R_R9 15 14 100 TC=0,0 R_R10 15 VMID 1e9 TC=0,0 R_R11 16 V++ 1 TC=0,0 R_R12 V-- 16 1 TC=0,0 * *2nd Gain Stage G_G3 V++ VG 16 VMID 24.893e-3 G_G4 V-- VG 16 VMID 24.893e-3 V_V5 19 VG .604 V_V6 VG 20 .604 D_D5 19 V++ DX D_D6 V-- 20 DX R_R13 VG V++ 636.658e3 TC=0,0 R_R14 V-- VG 636.658e3 TC=0,0 C_C2 VG V++ 2E-09 TC=0,0 C_C3 V-- VG 2E-09 TC=0,0 * *Mid supply Ref E_E4 VMID V-- V++ V-- 0.5 E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 I_ISY V+ V- DC 300e-6 * *Common Mode Gain Stage with Zero G_G5 V++ VC VCM VMID 2.5118E-10 G_G6 V-- VC VCM VMID 2.5118E-10 E_EOS 1 EN VC VMID 1 R_R15 VC 21 1e6 TC=0,0 R_R16 22 VC 1e6 TC=0,0 R_R22 EN VCM 5e11 TC=0,0 R_R23 VCM VIN- 5e11 TC=0,0 L_L1 21 V++ 1.9895 L_L2 22 V-- 1.9895 * *Pole Satge G_G7 V++ 23 VG VMID 376.98e-6 G_G8 V-- 23 VG VMID 376.98e-6 R_R17 23 V++ 2652.66 TC=0,0 R_R18 V-- 23 2652.66 TC=0,0 C_C4 23 V++ 10e-12 TC=0,0 C_C5 V-- 23 10e-12 TC=0,0 * *Output Stage with Correction Current Sources G_G9 26 V-- VOUT 23 0.02 G_G10 27 V-- 23 VOUT 0.02 G_G11 VOUT V++ V++ 23 0.02 G_G12 V-- VOUT 23 V-- 0.02 V_V7 24 VOUT .08 V_V8 VOUT 25 .08 D_D7 23 24 DX D_D8 25 23 DX D_D9 V++ 26 DX D_D10 V++ 27 DX D_D11 V-- 26 DY D_D12 V-- 27 DY R_R19 VOUT V++ 50 TC=0,0 R_R20 V-- VOUT 50 TC=0,0 .model pmosisil pmos (kp=16e-3 vto=-0.6) .model NCHANNELMOSFET nmos (kp=3e-3 vto=0.6) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28114subckt
FIGURE 21. SPICE NET LIST
12
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Characterization vs Simulation Results
INPUT NOISE VOLTAGE (nV/Hz)
INPUT NOISE VOLTAGE (nV/Hz) 10,000
1.0
(A) AC sims.dat (active)
V+ = 2.5V AV = 1
0.8
1000
0.6
0.4
100
0.2
10 1 10 100 1k FREQUENCY (Hz) 10k 100k
0 1.0
10
100
1.0k
10k
100k
FREQUENCY (Hz)
FIGURE 22. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 23. SIMULATED INPUT NOISE VOLTAGE
70 60 50 GAIN (dB) 40 30 20 10 0 AV = 10 AV = 100 AV = 1000
70 Rg = 100, Rf = 100k Rg = 1k, Rf = 100k GAIN (dB) V+ = 2.5V CL = 4pF RL = 10k VOUT = 50mVP-P 40 AV = 100 AV = 10 60 AV = 1000
(A) AC sims.dat (active) Rg = 100, Rf = 100k Rg = 1k, Rf = 100k
20
Rg = 10k, Rf = 100k AV = 1 Rg = OPEN, Rf = 0 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 0 -10
Rg = 10k, Rf = 100k Rg = 100k, Rf = 100k 10 100 1.0k 10k 100k 1.0M FREQUENCY (Hz) 10M 100M
-10 10
FIGURE 24. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 25. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
3 2 LARGE SIGNAL (V) 1 VS = 0.9V 0 -1 -2 -3 RL = 10k CL = 15pF AV = +1 VOUT = RAIL VS = 2.5V LARGE SIGNAL (V)
3 2 1
(A) AC sims.dat (active) VOUT VS = 2.5V
VIN -0 -1 -2 -3 V(VIN+)/VOUT)
RL = 10k CL = 15pF AV = +10 VOUT = RAIL 0 5 10 15 TIME (s) 20 25 30
0
1
2
3
4 5 6 TIME (s)
7
8
9
10
FIGURE 26. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = 0.9V, 2.5V
FIGURE 27. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs RL, VS = 0.9V, 2.5V
13
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Characterization vs Simulation Results (Continued)
100 OPEN LOOP GAIN (dB) 80 60 40 20 0 -20 V+ = 0.9V PHASE RL = 100k -40 CL = 10pF -60 SIMULATION -80 0.1 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) GAIN 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 10M 100M PHASE () OPEN LOOP GAIN (dB)/PHASE () 120 20 200 (A) AC2.dat (active) PHASE
160
120
80 GAIN RL = 10k 40 CL = 10pF MODEL VOS SET TO ZERO 0 FOR THIS TEST 0.01 0.1 1.0 10 100 1.0k 10k 100k 1M 10M 100M FREQUENCY (Hz)
FIGURE 28. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs FREQUENCY
FIGURE 29. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs FREQUENCY
80 70 60 50 40 30 20 10 SIMULATION 0 0.01 0.1 1 10 CMRR (dB ) CMRR (dB)
80
(A) AC sims.dat (active)
60
40
20
100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
0 0.01
0.1
1.0
10
100 1.0k 10k 100k 1.0M 10M 100M FREQUENCY (Hz)
FIGURE 30. SIMULATED (DESIGN) CMRR
FIGURE 31. SIMULATED (SPICE) CMRR
14
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you have the latest Rev. DATE 12/16/09 REVISION FN6800.3 CHANGE Removed "Coming Soon" from MSOP package options in the "Ordering Information" on page 2. Updated the Theta JA for the MSOP package option from 170C/W to 180C/W on page 4. Removed "Coming Soon" from SC70 and SOT-23 package options in the "Ordering Information" on page 2. Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice model (page 12). Initial Release
11/17/09 11/12/09 10/23/09
FN6800.2 FN6800.1 FN6800.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28114, ISL28214, ISL28414 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
15
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414 Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 5 0.25 Rev. 3 7/07 NOTES SYMBOL A MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053
5 E 1 2 3
4 C L C L E1
A1 A2 b b1 c c1
C
e
C L 0.20 (0.008) M C L C
b
D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0256 Ref 0.0512 Ref 0.010 0.018 0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o
0.65 Ref 1.30 Ref 0.26 0.46 0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 8o
0.10 (0.004) C
L2
WITH PLATING c
b b1 c1
N R R1 NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C 0.4mm L1
4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
0.75mm
2.1mm
0.65mm TYPICAL RECOMMENDED LAND PATTERN
16
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
17
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09
A 3.00.1 8 0.25 CAB
3.00.1
4.90.15
DETAIL "X"
1.10 Max PIN# 1 ID 1 2 0.65 BSC TOP VIEW B SIDE VIEW 2
0.18 0.05
0.95 BSC
0.860.09 H C SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B SIDE VIEW 1 0.10 0.05 0.10 C
GAUGE PLANE
0.25
33 0.55 0.15 DETAIL "X"
5.80 4.40 3.00
NOTES: 1. 2. 3. Dimensions are in millimeters. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. Plastic or metal protrusions of 0.15mm max per side are not included. Plastic interlead protrusions of 0.25mm max per side are not included. Dimensions "D" and "E1" are measured at Datum Plane "H". This replaces existing drawing # MDP0043 MSOP 8L.
0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN 5. 6. 4.
18
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09
4 4.90 0.10 A DETAIL "A" 0.22 0.03
B
6.0 0.20 3.90 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45 1.27 0.43 0.076 0.25 M C A B 4 4
SIDE VIEW "B" TOP VIEW
1.75 MAX
1.45 0.1 0.25 0.175 0.075 GAUGE PLANE C SEATING PLANE 0.10 C
SIDE VIEW "A
0.63 0.23
DETAIL "A"
(1.27) (0.60)
NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. 6. The pin #1 identifier may be either a mold or mark feature. Reference to JEDEC MS-012.
2. (5.40) 3. 4.
TYPICAL RECOMMENDED LAND PATTERN
19
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
20
FN6800.3 December 22, 2009
ISL28114, ISL28214, ISL28414 Thin Shrink Small Outline Package Family (TSSOP)
0.25 M C A B D N (N/2)+1 A
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
A A1 A2 b c D E E1 e
H
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 5.00 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 6.50 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 7.80 6.40 4.40 0.65 0.60 1.00
1.20 0.10 0.90 0.25 0.15 9.70 6.40 4.40 0.65 0.60 1.00
Max 0.05 0.05 +0.05/-0.06 +0.05/-0.06 0.10 Basic 0.10 Basic 0.15 Reference Rev. F 2/07
E
E1
1 B TOP VIEW
(N/2)
0.20 C B A 2X N/2 LEAD TIPS
C SEATING PLANE
e
0.05
L L1 NOTES:
b 0.10 C N LEADS SIDE VIEW
0.10 M C A B
1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X"
c
END VIEW
L1
A
A2 GAUGE PLANE 0.25 A1 DETAIL X L 0 - 8
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN6800.3 December 22, 2009

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